How to Smash the Memory Wall Plaguing High Performance Systems
The Next Platform, Wednesday, September 16th, 2026
A proposal to replace linear RAM addressing with Z-order layout to cut cache-coherency snoop traffic on many-core servers.
Analytical workloads on modern servers routinely fall short of peak theoretical performance because cores sit idle waiting on RAM.
The author argues the root cause is a forty-year-old architectural assumption that memory is a rigid one-dimensional array, while software deliberately clusters data by column and region.
When 128 cores request scattered 64-byte cache lines, maintaining coherency floods the interconnect with millions of broadcast snoop queries, gridlocking the bus exactly when it should be maximizing data throughput.
The piece models what changes if memory addresses are translated natively into Z-order, or Morton, layout, using the AMD Turin Epyc 9005 with 128 cores across 16 core complexes as the reference topology.